Non-volatile memory (NVM) refers to semiconductor memory devices having a number of cells which are able to store data (typically in the form of binary bits), and retain that data even when the supply of electricity is removed from the device containing the NVM cells.
Flash memory is an example of non-volatile memory. Generally, data may be “programmed” into an array of NVM cells, and the array may be divided into blocks, pages, and other sub-divisions of the array. The data which is stored in the NVM array may subsequently be “read”. Before programming new data in, for example, a block of NVM, all of the cells in the block are typically “erased”.
An example of a volatile semiconductor memory device, which also has a number of cells which are able to store data (typically in the form of binary bits), but which loses its data when the power is removed, is static random access memory (SRAM). Generally, data may be “written” (rather than “programmed) to the cells of SRAM. (However, for NVM and SRAM, the terms “write” and “program” (and grammatical variations thereof) are often used, and may be used herein interchangeably.) The data which is stored in the SRAM may subsequently be “read”.
Non-Volatile Memory Cells, Generally
In the main, hereinafter, nonvolatile memory (NVM) cells such as such as floating gate (FG) devices or charge-trapping devices such as nitride read only memory (NROM) may be discussed. Both of these NVM devices are similar to a field effect transistor (FET) which has source (S) and drain (D) diffusions in a semiconductor substrate, separated by a channel, and a gate element (G) disposed above the channel in the substrate and separated therefrom by a an insulating layer (gate oxide).
A floating gate (FG) device is similar to a field effect transistor (FET), but with a charge storage layer (floating gate) substituted for the gate oxide between the gate element and the underlying substrate. The charge storage layer may comprise a conductor, such as polysilicon, which is insulated from the gate element above and the substrate below by oxide. Charges in the charge storage layer are free to move around, since it is a conductor.
A nitride read only memory (NROM) is similar to a field effect transistor (FET), but with a charge trapping layer substituted for the gate oxide between the gate element and the substrate. The charge trapping layer may comprise a non-conductive, charge-trapping layer disposed between the gate element and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate element.
Because the nitride layer in an NROM device is not a conductor, but rather “traps” charges, there may be two distinct charge-trapping areas in the nitride layer, one above each of the source and drain diffusions of the cell, and these may be referred to as the “left” and “right” charge storage areas, sometimes also referred to as left and right “bits” of the memory cell. These two charge storage areas may also be referred to as “half cells”—one NROM cell comprising two half cells which can independently be programmed and read.
Generally, there are three “modes of operation” for NVM cells: “program”, “erase”, and read”. “Program” may involve applying appropriate voltages to the terminals of the memory cell to cause injection of electrons into the charge storage layer of FG, or selected areas the charge trapping layer of NROM, such as by a process known as channel hot electron (CHE) injection. As the number of electrons increased, the threshold voltage (Vt) of the charge storage layer of FG or selected areas the charge trapping layer of NROM increases. Very generally, different threshold voltages (Vt's), or ranges thereof, may be associated with different “program levels”. “Erase” may involve applying appropriate voltages to the terminals of the memory cell to cause F-N tunneling of electrons out of the charge storage layer of FG, or hot hole injection (HHI) of holes into selected areas the charge trapping layer of NROM. (Generally, “holes” are electrically opposite to electrons, and “cancel them out”.) As electrons are removed or canceled out, the threshold voltage decreases. “Read” may involve applying appropriate voltages to the terminals of the memory cell, and based on subsequent current flow, ascertaining (measuring) the threshold voltage of the charge storage layer of FG, or selected areas the charge trapping layer of NROM.
Memory Array Architecture, Generally
Memory arrays are well known, and may comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
Generally, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate. Different voltages may be applied to each of the source, drain and gate to operate the memory cell. Generally, a first one of the diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 1A illustrates an array of NVM memory cells (labeled “a” through “i”), which may be of the NROM charge-trapping type, connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 1A are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell.
The bitlines (BLs) mentioned above may extend in parallel with one another, through the array (or a portion thereof). A single buried bitline (BB) may be a single diffusion shared by two adjacent cell transistors, and may be referred to herein as a diffusion bitline (DBL). The diffusion bitline (DBL) is a diffusion, functioning as a conductive line, which is physically disposed (“buried”) within the surface of the substrate.
Programming Data, Generally
Programming data into a non-volatile memory (NVM) mass storage device (sometimes referred to as “writing”) may comprise applying appropriate voltages to selected ones of the bitlines and wordlines, thereby injecting electrons into the charge storage or charge trapping layer of selected memory cells in an array to increase the threshold voltage (Vt) of the selected memory cells.
Generally, different threshold voltage levels are associated with and represent different data values. For example, when there are two “program levels”, one program level may represent binary “0”, and the other program level may represent binary “1”.
Programming these bits typically comprises asserting one or more programming pulses, each increasing a given NVM cell's Vt by a small increment, followed by a verification phase in which the bits are read to determine (verify) whether the cells have been successfully programmed. Multiple cycles of program pulses followed by verify may be needed to complete programming all the bits.
Generally, programming is performed by first writing the data into a memory element such as a static random access memory (SRAM) device which may operate faster than NVM, then using the data in the SRAM to control programming of corresponding memory cells in the array of NVM cells. Generally, by caching the data to be written, controller (microprocessor) resources are freed up to work on other things.
FIG. 1B illustrates, in a very general manner, the concept that data is “buffered” in cache memory (such as SRAM) prior to being written to an NVM array (such as the NROM array shown in FIG. 1A) and when being read from the NVM array. The data may be in the form of a data stream which is accumulated by the SRAM into blocks, prior to writing to the NVM array. The SRAM may also serialize chunks of data which are read from the NVM array. The cache memory may be on the same chip as the NVM array.
Cache Operation
Cache programming generally refers to the practice of putting a cache memory before the memory array. Otherwise referred to as “pipelining”, a page of data may be input to a cache register, then this data is transferred to a data register when a cache programming command is issued. When the transfer is complete, the cache register is available to receive new data input, while the data register simultaneously programs the memory array.
A normal cache programming operation requires two buffers, one working with the user and the other working with the array. The data to be programmed to the NVM array is loaded by the user (which may be a software application) and temporarily stored in a volatile data buffer such as SRAM array. After applying a programming pulse, the data read out from the NVM array is usually stored in a second volatile buffer, and program verification is carried out by comparing the data of the two buffers (the original data to be programmed and the temporarily read out data).
Cache programming may use a page-size cache register to program pages of data within a block. In the standard page program operation, the device has to finish programming the data into the memory array before a new page can be programmed. The advantage of the cache program operation is that it allows new data to be input while the previous data, that was transferred to the page buffer, is programmed into the memory array.
Program/Verify Cycle
Programming is typically performed in increments, with pulses of voltage—after each pulse, a verify operation occurs in which the threshold voltage level of the cell is measured (read). The general idea is to “nudge” the threshold voltage to the desired level, rather than over-shooting (over programming) or under-shooting (under programming) the desired level. With appropriate control mechanisms, only a few pulses (nudges) are required. A similar concept of cycles of pulse followed by verify until a desired Vt has been attained may sometimes be used during the erase operation, to avoid under-erase or over-erase. See, for example, commonly-owned U.S. Pat. Nos. 6,292,394; 6,396,741; 6,490,204; 6,552,387; 6,636,440; and 6,643,181.
On Reading the State of the Memory Cells
A memory cell may be programmed to different states, or program levels, determined by the threshold voltage (Vt) of the cell. For a single level cell (SLC), there are two program levels, generally “erase” and “program”. For a multi-level cell (MLC) there are more than two program levels. An NVM cell's state may be defined and determined by its threshold voltage (Vt), the voltage at which the cell begins to conduct current. A NVM cell's threshold voltage level is usually correlated to the amount of charge stored in a charge storage layer or charge trapping region of the cell. Different threshold voltage ranges are associated with different states or program levels of an NVM cell.
Generally, in order to determine the state (program level) of an NVM cell, the cell's threshold level may be compared to that of a reference structure or cell whose threshold level is set, or otherwise known to be, at a voltage level associated with the specific state being tested for. Comparing the threshold voltage of a NVM cell to that of a reference cell is often accomplished using a sense amplifier or similar circuit. Various techniques for comparing an NVM cell's threshold voltage against those of one or more reference cells or structures, in order to determine the NVM cell's state, are well known.
When reading a NVM cell, to determine whether it is at a particular state, the cell's threshold voltage may be compared against that of a reference cell having a reference threshold voltage defined as a “read” level for the specific state. A “read” level is usually set lower than a program verify (PV) level and higher than the erase verify (EV) level in order to compensate for threshold voltage (Vt) drifts which may occur during operation.
In a “binary” or single level cell (SLC) capable of storing only one bit of information (a logic 1 or a logic 0), only a single read verify (RV) voltage is required, and it may be between the erase verify (EV) and program verify (PV) voltages for the cell.
“Read” is generally done by measuring the Vt of a cell (or half-cell), and associating the measured Vt with a program level (such as “0” or “1”). Although the Vt's of the cells are measured on an individual basis, it is generally necessary to determine a distribution of Vt's for many cells in order to associate the measured Vt of a given cell with a program level, with confidence. For example—if only one cell were to be read, and its threshold voltage were to be found to be at or very near the RV between two program levels, it may be difficult to say, with certainty, at which of two program levels the single cell was programmed, since its threshold voltage may have moved slightly upward or slightly downward since it was programmed. This is a benefit of reading bits one block at a time—to obtain a statistically meaningful sample of Vt's across a number of cells.
Threshold Voltage Drift
The threshold voltage of a NVM cell seldom stays fixed (after it is programmed, or erased). Threshold voltage drift is a phenomenon which may result in large variations of the threshold voltage of a memory cell. These variations may occur due to charge leakage from the cell's charge storage region, temperature changes, and due to interference from the operation of neighboring NVM cells.
The drift in threshold voltage of a memory cell is well known, and is discussed for example in commonly-owned U.S. Pat. Nos. 6,992,932 and 6,963,505 discloses read error detection in a NVM array, and may hereinafter be referred to as the “moving read reference” patent(s). These deviations in a cell's threshold voltage (Vt) may be either in the upward or downward direction, and may vary from cell to cell.
Variation of the threshold voltage of memory cells may lead to false reads of the cell's state and may further result in the corruption of the data in the memory array. Voltage drift is especially problematic in MLC cells (see FIG. 2B) where the Vt regions or sub-ranges associated with each programmed state are relatively smaller than those for a typical binary or SLC cell (see FIG. 2A).
It is known that, in order to reduce data loss and data corruption due to drift in the threshold voltages of the cells of a NVM array, threshold voltage drift of cells in the NVM array should be compensated for, during the read process.
The moving read reference patents disclose that, for a given NVM array, it is known to provide one or a set of reference cells whose references threshold voltages are offset from defined verify threshold levels by some value related to the actual threshold voltage drift experienced by the NVM cells to be read. There is a well understood need for an efficient and reliable method of determining a set of reference voltage levels which may accommodate variations in the threshold voltages of cells of an NVM array, and of established reference cells with the determined reference voltages.
On the Use of Reference Cells
Non-volatile memory (NVM) cells may have data bits stored therein that may be read, such as by means of a sense amplifier (SA). When reading a memory cell, a current flowing into the drain or out of the source may be measured, in order to determine the Vt of the charge storage area above the source (or, in the case of a floating gate memory cell, the Vt of the floating gate), and a voltage may be ascertained which corresponds to a program level.
Many NVM arrays employ a “reference cell” as the basis for comparing the output of an “array cell” for a read operation. Both of these cells—the reference cell and the array cell—are memory cells, such as flash cells, and may be substantially identical with one another, although they may be located in different portions of the overall memory array (and, of course, on the same integrated circuit (IC) chip). The use of a reference cell may help compensate for changes in the overall array, such as due to voltage variations and temperature, and ensure a fairly stable reference for read operations.
Reference cells are memory cells that are programmed to one or more predetermined levels related to reading the contents (program level, data bits stored in) of the array cells. See, for example, commonly-owned U.S. Pat. Nos. 7,123,532 and 6,954,393.
Using reference cells to determine the program level of an array cell being read is somewhat analogous to “color matching”. For example, when a dentist is trying to determine a patient's tooth color, for manufacturing a prosthetic (false tooth), he may hold a card with reference colors (generally, all slightly different shades of white) up against the patient's tooth, comparing the reference colors to the patient's tooth color, looking for the best match. When holding a color sample against the patient's tooth, the dentist may determine that the tooth is either lighter than or darker than the color sample.
In the context of reading using reference cells, usually a value for Vt obtained from an array cell being read is compared against a “known” value from a reference cell and, using the sense amplifier (SA), it is determined whether the value read from the array cell is greater than the value retrieved from the reference cell. It is generally very important that the paths leading from the sense amps to the array cells are “matched” with the paths to the reference cells, and that they are operated in the same manner (for example, using the same drain drivers and Vds to read reference cells as are used to read the array cells.)
Adjusting/Shifting Read Reference Voltages/on the Use of ED Bits
Prior to or during the programming of a set of cells in a NVM array, the number of cells to be programmed to each of one or more logical or program states associated with the set of cells may be counted, and may be counted and stored, for example in a check sum table. The number of cells to be programmed to, up to and/or below each logical or program state may be counted and/or stored in the table which is either on the same array as the set of NVM cells or in memory on the same chip as the NVM array.
When reading the programmed array cells, the number of cells found to be at a given logical or program state may be compared against either corresponding values stored during programming (such as the number of cells programmed to a given state) or against a value derived from the values stored during programming (such as the number of cells programmed at or above the given state, minus the number of cells programmed to or above an adjacent higher logical state).
Generally, in the case of counting the number of cells programmed to a given state, the number stored is an error detection (ED) value, and the process of using this ED value (or stored ED bits) to correct a faulty read may be referred to as the “ED mechanism”.
If there is a discrepancy between the number of cells read at a given state and an expected number based on the values determined/counted/stored during programming, a read voltage (RD, also referred to as Read Verify (RV) voltage) associated with the given program state may be adjusted upward or downward to compensate for the detected error. The read verify level of an adjacent logical state may also be moved upward or downward in order to compensate for detected read errors at a given state.
For example, if the number of cells found (read) in a given program state is below an expected value, either the Read Verify voltage associated with that given state may be reduced, or if there is found that the number of cells read above the given state exceeds an expected number, the Read Verify voltage associated with a logical state higher and adjacent to the given state may be raised. Conversely, if the number of cells found. (e.g. read) in a given program state is above expectations, either the Read Verify voltage/value associated with that given state may be increased, or if there is found that the number of cells read above the given state is below an expected number, the Read Verify voltage associated with a logical state higher and adjacent to the given state may be lowered. Thus, Read Verify voltages for a set of cells may be selected such that the number of cells found/read in each of the states associated with the set may be substantially equal to the a number either read from or derived from the values counted during programming of the set of cells, which values may have been stored in a check sum table.
The check sum table (or ED bits) may reside on the same chip as the set of NVM cells, and a controller may be adapted to perform the above mentioned error detection and Read Verify reference value adjustments. The check sum table may either be stored in the same NVM array as the set of NVM cells, or on some other memory cells residing on the same chip as the NVM array, for example in a register or buffer used by the controller during programming and/or reading. Specialized error coding and detection circuits may be included with a controller on the same chip and the NVM array to be operated.
During the reading of the cells from the programmed set of cells, either the controller or some other error detection circuit may compare the number of cells counted in each program state during reading with the correspond check sum values stored during or prior to programming. For example, if the number of cells found in a given program state exceed the value derived from the check sum values, the Read Verify voltage associated with that given program state may be raised or the Read Verify voltage associated with the adjacent higher state may be lowered. Conversely, if the number of cell's found in a given program state is below the expected number, either the read verify threshold value associated with the given program state may be lowered, or the read verify threshold value associated with the next higher adjacent state may be raised.
If the number of cells found (read) in a given program state is below an expected value, either the Read Verify reference voltage associated with that given state may be reduced, or if there is found that the number of cells read above the given state exceeds an expected number, the Read Verify reference associated with a logical state higher and adjacent to the given state may be raised. Conversely, if the number of cells found (e.g. read) in a given program state is above expectations, either the Read Verify voltage associated with that given state may be increased, or if there is found that the number of cells read above the given state is below an expected number, the Read Verify voltage associated with a logical state higher and adjacent to the given state may be lowered.
Thus, Read Verify reference voltages for a set of cells may be selected such that the number of cells found/read in each of the states associated with the set may be substantially equal to the a number either read from or derived from the values counted during programming of the set of cells, which values may have been stored in a check sum table.
The steps described hereinabove may be repeated as part of an iterative process until the number of cells read in each program state substantially corresponds to the number of cells expected in each state based on data recorded during programming. The process may start with the checking of cells programmed to the highest logical state, or cells programmed to several different states may be checked in parallel.
ED bits may be programmed into multi-level cells in a “high reliable” manner, to reduce problems associated with threshold voltage shift. For example, in memory cells having four accessible program levels, such as shown in FIG. 2B, the ED bits may be programmed using only two widely separated levels, such as “11” (the lowest threshold voltages) and “10” (the highest threshold voltage), so that there is a wide gap between the two threshold voltage distributions and the ED bits can reliably be read.
Operating Flash Memory
Flash is a non-volatile memory that can retain the data stored therein even after power is removed. NAND Flash (see Glossary below), which is one type of Flash, is a high-density design and has certain advantages over other types of memory, including a large storage capacity (such as one giga-bits or more), good speed for continued access, and low cost. However, NAND Flash also has several inherent drawbacks, including poor performance for random access and increased susceptibility to bit errors over the NAND Flash's operating lifetime. In particular, NAND Flash is typically accessed in unit of pages, one page at a time, with each page being of a particular size (such as 512 bytes).
Because the structure of NAND Flash is not suitable for random access, program codes cannot be executed directly from the NAND Flash. Instead, Static Random Access Memory (SRAM) may be used as an intermediate storage for data and program codes that need to be accessed in a random manner by the processor. A memory architecture that incorporates both SRAM and NAND Flash may thus provide large storage capacity, reduced cost, and random access.
Conventionally, reading data from or writing data into NAND Flash requires excessive involvement and control by the processor. This can tie up the processor and prevents it from performing other functions, which can then result in overall performance degradation for the communication device. Moreover, since NAND Flash is more prone to bit errors, a mechanism is needed to ensure data integrity when loading data from or into the NAND Flash.
As described, for example, in commonly-owned U.S. Pat. No. 6,967,896, a user wishing to write data to a NVM array may typically write the data to a cache memory, such as but not limited to, a static random access memory (SRAM). The cache memory routes or “addresses” the data to the appropriate bits in the NVM array. The data may be written to the SRAM in a byte granularity.
Array Architecture (and Operation)
FIG. 1C is a diagram of a mass storage device 150 such as such as non-volatile memory (NVM) which may comprise at least one array 152 of NVM memory cells, such as FG or NROM cells. Compare, for example, commonly-owned U.S. Pat. No. 7,062,619, which discloses mass storage device architecture and operation.
An X-decoder (XDEC) 154 may select and drive word lines within the array. A decoding control unit (DEC) 156 and one or more data path units (DPU) 158 may be disposed peripheral to the Array 152.
The decoding control unit 156 may control data coding/decoding operations related to the transfer of information to and from the NVM cells in the Array 152, such as but not limited to, selecting blocks or physical sectors, transfer of voltages and currents, and control of some operations of the data path units 158, such as enabling different signal paths to and from the NVM array.
The data path unit 158 may comprise a YMUX (y-multiplexer) to select one or more bit lines of the Array 152. The data path unit 158 may further comprise driving units (not shown) that drive the bit-lines in different operational modes (such as read, program, erase), sensing circuitry to generate a logical signal out of the array signals, a redundancy multiplexer to support column redundancy, as well as other components.
The various elements Array 152, XDEC 154, DEC 156 and DPU 158 may be generally laid out, as shown, but it should be understood that this drawing is a schematic representation. The Array 152 will generally be much larger (physically, size-wise) than any of the XDEC 154, DEC 156 or DPU 158.
A data bus 160 may transfer data between the data path unit(s) 158 and a plurality of other units, such as but not limited to, a buffer interface unit (BIF, not shown), a redundancy unit (not shown), a built-in self-test unit (BIST, not shown). A controller 170 may interface with the data bus 160 via these other units (not shown). The data bus 160 may also transfer data back and forth to static random access memory (SRAM) 162. A user (another device) may input data and communicate with (control) the controller 170 via an input/output (I/O) unit 172.
In general, programming operations performed on the Array 152 may comprise writing data, which has been stored in a first portion of SRAM 162, to bits in array 152.
A user may choose to program bits of the Array 152 by application of the necessary word line and bit line voltages. However, it may be advantageous before applying these voltages to verify if the bits have already reached a programmed state. If a bit is already programmed, then application of the programming voltages may be a waste of time and power, and may detrimentally affect the reliability of the memory cells. Accordingly, prior to programming, the state of a particular bit may be pre-verified to detect whether the bit is in a programmed state or not.
Consider the example of “0” representing an erase state, and “1” representing a program state. First, all the bits in the Array are erased. Then, based on the User Data in the SRAM, the SRAM bits which are ‘0’ are programmed into corresponding bits in the Array. When it is verified that an Array bit has reached its programmed state, the SRAM bit can be changed to ‘1’, to stop programming of the corresponding Array bit. Generally, during programming once all the bits of SRAM 162 are ‘1’, it is a sign that all of the bits of the array 152 which should be programmed are programmed, and no further programming is required.
After or while writing data to the Array 152, the operation may fail to reach completion, for whatever reason. As a result, the data SRAM may contain 0's, but not necessarily as in the original data (some of the 1's in the data SRAM may correspond to bits that completed their programming prior the operation failure).
Single-Level and Multi-Level Programming
In early NVM memory cells, there were generally only two program levels (or states), which represented binary “0” and binary “1”, and this is referred to as “single level programming” (SLC). Generally, the program level is determined by the threshold voltage created by electrons (or holes) stored in the floating gate (of an FG cell) or in the charge-trapping medium (such as nitride layer, in NROM). For example, a binary “0” may have been represented by a threshold voltage (Vt) less than 4.0 volts, and a binary “1” may have been represented by a threshold voltage greater than 4.0 volts.
FIG. 2A is a graph illustrating two states of a “binary” or single level cell (SLC) capable of storing one bit of information per cell (or per charge trapping area with an NROM cell), and utilizes only one read verify threshold (RV). Generally, the two states are erased (represented by “1”) and programmed (represented by “0”). The horizontal axis is threshold voltage (Vt), increasing from left to right.
Three voltage levels are illustrated in FIG. 2A, these are EV (erase verify), RV (read verify) and PV (program verify). As illustrated, EV is less than RV which is less than PV. A high Vt may represent a program state of binary “0”, and a low Vt may represent an erase state of binary “1”. The binary designations are arbitrary, and may be reversed (high Vt=“1”, low Vt=“0”).
FIG. 2A is generalized, and is applicable to a population (plurality) of memory cells (or half cells). The curves represent the threshold voltages (Vts) for a number of cells at the given program level. Typically, there is a distribution, or spread, about a nominal (or average, or center) value. For example,                the center value for “1” equals approximately 3.5 volts        the center value for “0” equals approximately 6.0 volts        EV equals approximately 4.0 volts        RV equals approximately 4.5 volts        PV equals approximately 5.5 volts        
In modern NVM memory cells, four or more program levels are possible, representing for example, binary “00” (zero), binary “01” (one), binary “10” (two) and binary “11” (three). This (having more than two program levels) is referred to as “multi-level programming” (MLC), and exemplary threshold voltages representing these four program levels might be, for example:                the center value for “11” equals approximately 4.0 volts        the center value for “01” equals approximately 4.4 volts        the center value for “00” equals approximately 4.8 volts        the center value for “10” equals approximately 5.4 volts        
Thus, it is evident that multi-level programming is much more “sensitive” than single level programming and, when reading the contents of a memory cell, small changes in threshold voltage or differences in measured voltage can lead to erroneous results.
Two binary digits, or “places” can represent four numbers. A “normal” binary counting sequence would be 00, 01, 10, 11, corresponding to decimal 0,1,2,3. Since it is arbitrary, which program levels represent which digits, notice in FIG. 2B that the program levels appear to be out of sequence, starting with 11 (three), then 01 (one), then 00 (zero), then 10 (two). This sequence 11, 01, 11, 10 appears to be not only reversed (starting with the highest binary value “11”), but also out of order, and is illustrative of a Gray code which, is a binary numeral system where two successive values may differ in only one digit. (In the “normal” binary counting sequence, both digits change when going from 01 to 10.) There are technical reasons for this, and the sequence may be considered to be arbitrary for purposes of the descriptions set forth herein.
FIG. 2B illustrates a situation wherein there are four possible MLC program levels (or states) 11, 01, 00, 10 for each memory cell (or, in the case of NROM, for each storage area of the memory cell). As illustrated, the program level 11 has the lowest Vt, the program level 01 has a higher Vt, the program level 00 has a yet higher Vt, and the program level 10 has a yet higher Vt. The program level 11 may be erase (ERS), which for purposes of this discussion is considered to be a program level, although it is not generally regarded as such.
There are a number of memory cells (or storage areas NROM cells) being programmed, erased and read. In a given array, or on a given memory chip, there may be many millions of memory cells. Programming may typically be performed in blocks, of thousands of memory cells. The different blocks of memory cells are typically located at different logical positions within the array, and at different physical positions on the chip. During (or before) programming, a checksum indicative of the number of cells programmed to each level may be stored, in the block, in the array, on the chip, or external to the chip.
At each program level (and this is also true for the SLC cells or half cells of FIG. 2A), there is typically a distribution of threshold voltages, within a range (a statistical spread). In other words, for a given program level, the threshold voltage is not likely to be exactly a unique, precise voltage for all of the memory cells being programmed to that level. Initially, in the act of programming the cell, the voltage may be off a bit, for example as a result of the state of neighboring cells (or the other charge storage area in the same NROM cell). Or, as a result of previous program or erase operations on the same cell, or neighboring cells. Or, as a result of a variety of other factors. And, after programming, the threshold voltage of a cell may change, as a result of programming neighboring cells (or the other charge storage area in the same NROM cell), or a variety of other factors.
Therefore, the threshold voltage (Vt) for a given program level may be more than average in some cells, in others it may be less than average. Neertheless, in a properly functioning group of cells (such as a block, or an array), there should be a clear distribution of four distinct program levels, such as illustrated. And, the distributions of Vt for each of the program levels should be separated enough from one another so that read positions (RV voltage levels) can be established between adjacent distributions of threshold voltages, such as the following:                RV01 is between EV and PV01, or higher than the highest expected Vt for a cell at state “11” and lower than the lowest expected Vt for a cell at state “01”;        RV00 is between PV01 and PV00, or higher than the highest expected Vt for a cell at state “01” and lower than the lowest expected Vt for a cell at state “00”; and        RV 10 is between PV00 and PV10, or higher than the highest expected Vt for a cell at state “00” and lower than the lowest expected Vt for a cell at state “10”.        
For example,                the center value for “11” equals approximately 4.0 volts        the center value for “01” equals approximately 4.4 volts        the center value for “00” equals approximately 4.8 volts        the center value for “10” equals approximately 5.4 volts        EV equals approximately 4.0 volts        RV01 equals approximately 4.4 volts        PV01 equals approximately 4.8 volts        RV00 equals approximately 5.4 volts        PV00 equals approximately 5.6 volts        RV00 equals approximately 6.0 volts        PV10 equals approximately 6.3 voltsThreshold Voltage Drift        
FIG. 2C illustrates a condition of a pollution of NVM cells, programmed with SLC, wherein some of the bits (cells) in the higher “0” distribution have dropped below the RD level. In such a case, these cells below RD will not be read as “0s”, but rather will be inferred to be “1s”. (Commonly, the erased cells, in this case the “1s” are not counted, but are “inferred” simply by subtracting the number of “0s” from the total number of “1s” and “0s”.)
FIG. 2C illustrates how to “capture” the low Vt “0s”. This generally involves simply moving the read reference (RD), to the left, now labeled RD′ (prime), to “capture” the “0s” that have lost sufficient Vt to be below the initial RD value. (It may be assumed that the Vt of these cells is still above the “1” (erase) distribution.) This may be referred to as “moving read reference”, and the concept is generally disclosed in the aforementioned commonly-owned U.S. Pat. Nos. 6,963,505 and 6,992,932.
Generally, the decision to move RD may be based on having counted the number of “0s” which were programmed, and storing that number as an error detection (ED) bits. The recovered (read from the array) data is counted and compared to the stored ED bits. When, for example, fewer “0s” are read than were stored, this may indicate using what may be referred to herein as the “ED mechanism” to shift the read reference (RD) to the left, to caputure the “missing” “0s”.
Two-Phase Programming
A MLC programming algorithm may include 2 phases, which may generally be referred to as “Phase 1” and “Phase 2”, each phase operating like a normal two bit programming algorithm. For example, in Phase 1, which may be considered to be a “rough” phase, user data may quickly be programmed, in a series of “rough” increments, to an initial level (Vi) which is below a target level (Vt). Once all the data is above the initial level (Vi), in the second phase (Phase 2), the same data may be programmed again (or “re-programmed”) to the target levels (Vt's), which may be considered to be a “fine” phase. In Phase 2, some of the cells will already be at the target level from the Phase 1 programming, and may not need to be re-programmed. Because of the two phases, the programming operation may use two (2) buffers, and each of the two buffers may be implemented in SRAM. These 2 buffers are required on top of the cache programming functionality requirement for two buffers as well. See, for example, Flash Memory Trends & Perspectives, Geoffrey MacGillivray, Semiconductor Insights, 2006 (page 11, Toshiba Programming Algorithm. Two-phase scheme to reduce programming time), incorporated in its entirety by reference herein.
It may be appreciated that although everything could be done in a single (one) phase of fine increments, the two phase approach (rough increments followed by fine increments) can achieve the desired Vt's without overshooting more efficiently and more quickly.
Recovery of User Data
Generally, when programming user data to a NVM array, the user data may first be written to a buffer, such as an SRAM, a process which may proceed much more quickly and reliably than programming the Array. The SRAM initially contains a valid copy of the user data. Generally, each bit (address) of the SRAM corresponds to a bit (address) of the array.
Just as an example, to program one page of an NVM array may be performed in a number of steps (for example, in two-phase programming) and may take about 1 msec (millisecond, or thousandth of a second), and to write a comparable amount of SRAM may be performed in one step and may take about 5 μsec (microseconds, or millionths of seconds). (In this example, SRAM can be written approximately 200 times faster than NVM can be programmed.)
Programming the cells of an NVM array may proceed in steps, using a limited number of pulses to nudge the threshold voltages (Vt's) of the cells above a program verify (PV) value. During programming, the SRAM may be used to control the operation of programming corresponding NVM cells of the array. Generally, the contents of the SRAM may change as array cells become successfully programmed (some addresses/bits of the SRAM may be re-written). Hopefully, all of the NVM cells will be successfully programmed, at which point the contents of the SRAM can be flushed, and filled (written) with new user data for controlling the programming of other NVM cells.
Programming NVM array cells may not always be successful, and may need to be re-done. However, due to the nature of how programming the NVM array cells typically proceeds (with the SRAM being re-written during programming), the user data may be “lost” in the midst of the process. Consequently, the original user data needs to be “recovered”, or “reconstructed”. (Else, it would need to be re-supplied/re-inserted by the user.)
Additional Background Information
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750. See also commonly-owned U.S. Pat. No. 7,062,619.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, Vol. 1 & 2 (2005), Vol. 3 (2006) and Vol. 4 (2007), published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at:    http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at:    http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at:    http://www.research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at:    http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.